FPGA / Digital Design Engineer
Foundry Nine · Semiconductors
RTL for a RISC-V inference accelerator, two tape-outs a year.
Hardware / FPGA / ASICSenior (5–9 yrs)HybridPermanentSponsors visas
Salary band
£70,000 – £90,000
0.05–0.25% options
- Location
- Belfast
- Pattern
- Hybrid
- Posted
- 27 Aug 2026 (7d ago)
- Process
- 3 stages, listed below
No account needed. One of us reads it before anything reaches the company.
The work
The accelerator does int8 inference at the edge with a hard power budget. Most decisions come back to that budget.
Worth knowing
- Two days in Belfast, the rest remote.
- Verification is the majority of the work and is treated as senior work.
Must have
- RTL design taken to silicon or a shipping FPGA product
- Verification as part of design
- Timing closure
Nice to have
- RISC-V
- Systolic arrays or dataflow accelerators
Interview process
If the client adds a stage after you’ve started, we’ll tell you, and you can withdraw.
- 01
Intro call
30 minTheir questions and yours. No competency framework.
- 02
Technical conversation
60 minWalk through something you built. No live coding.
- 03
Team and offer
45 minMeet the people you would work with, talk numbers.